Appeal No. 1998-2712
Application No. 08/478,429
In short, we adopt appellant’s position, at page 10 of the principal brief, wherein
appellant argues that
neither Szczepanek nor Phelps disclose or suggest [sic, discloses or suggests]
use of a memory means for storing the row addresses of each memory row
containing data matching the input value. Szczepanek, upon finding a match,
immediately gates the address of the bit onto the address/data bus. Phelps
uses a single match line to initiate a shuffle of the matching memory row to
the first row in the array. Both Szczepanek and Phelps assume that only one
match will be found in the memory contents. Neither suggest [sic, suggests]
providing a means for storing the row addresses of multiple matches.
Accordingly, the examiner’s decision rejecting claim 15 under 35 U.S.C.
§§ 102/103 over Phelps and claims 1 and 3-16 under 35 U.S.C. § 103 over
Szczepanek and Phelps is reversed.
REVERSED
JAMES D. THOMAS )
Administrative Patent Judge )
)
)
)
) BOARD OF PATENT
ERROL A. KRASS ) APPEALS
Administrative Patent Judge ) AND
) INTERFERENCES
)
)
)
JERRY SMITH )
Administrative Patent Judge )
7
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007