Appeal No. 1998-2749
Application 08/637,062
With respect to claim 28, Appellant argues that the Examiner
has made no showing that any of the references adds status and
length fields at the beginning of a frame when the frame is
completely loaded (Br7). The Examiner states that it is inherent
that the status and length fields are added at the beginning of a
frame when the frame is completely loaded, referring to column 4,
lines 5-19 (EA7).
We fail to see how Hausman inherently discloses adding status
and length fields at the beginning of a frame when the frame is
completely loaded. Figure 3B, to which the Examiner refers, deals
with the format of a receive packet 320. Although the receive
packet 320 has status and length fields, these are part of the
packet as received and are not added when the frame (packet) is
completely loaded and are not added to the beginning of the frame.
Accordingly, we find that claim 28 is not anticipated. The
rejection of claim 28 is reversed.
Appellant argues that, with respect to claim 29, the Examiner
has not shown a DMA circuit in which DMA access logic is provided
on chip and the DMA controller is provided off chip and, with
respect to claim 30, the Examiner has not shown an architecture in
which the internal buffer memory is provided on chip (Br7). The
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