Appeal No. 1998-2749
Application 08/637,062
Claims 15-18
The Examiner finds that Hausman does not explicitly teach
generating addresses to allow the host processor to read data
frames from the memory buffer, but finds Petersen teaches using
host interface logic for transferring data between the host system
memory and adapter memory, referring to Host Interface Logic 102,
figure 5 (Paper No. 2, p. 5). The Examiner concludes with respect
to claim 15 (Paper No. 2, pp. 5-6):
It would have been obvious . . . to combine the
teachings of Hausman to provide Petersen's Host Interface
Logic for generating addresses to allow data transfer between
said host system memory and said memory buffer because it
would reduce host processor interrupt latency.
Appellant argues that the addressing scheme in Petersen has
nothing to do with reducing processor interrupt latency and, thus,
the Examiner's rationale is not appropriate (Br7-8).
We are not persuaded by the Examiner's reasoning using
Petersen. While Petersen discloses a host interface logic 102
which is responsive to accesses across the host bus to operate to
transfer data between the specified block of addresses 101 in the
host memory space and the independent memory (col. 12,
lines 22-32), we fail to see how this suggests modifying Hausman
to arrive at the claimed subject matter of claim 15. Accordingly,
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