Appeal No. 1999-0014
Application No. 08/748,123
bits. Claim 1 is illustrative of the claimed invention, and
it reads as follows:
1. A computer processor comprising:
a register file including a plurality of physical
registers; and,
an execution unit that executes bit scan instructions,
coupled to the register file and having a leading/trailing
zero detector circuit for receiving a source operand from the
register file and detecting in parallel, which bit positions
in the source operand are non-zero, and providing an output
destination index having a plurality of bits, to indicate a
first non-zero bit position in the source operand wherein the
plurality of bits of the output destination index are
simultaneously calculated and presented in parallel without
requiring resolution of any of the plurality of bits before
resolving any other of the plurality of bits.
The prior art references of record relied upon by the
examiner in rejecting the appealed claims are:
Hannai 4,833,348 May 23,
1989
Watanabe et al. (Watanabe) 5,091,874 Feb. 25,
1992
Claims 1 through 3, 5, 7 through 10, 12 through 16, and
18 through 21 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Watanabe.
2
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