Appeal No. 1999-0014
Application No. 08/748,123
Claim 6 stands rejected under 35 U.S.C. § 103 as being
unpatentable over Watanabe in view of Hannai.
Reference is made to the Examiner's Answer (Paper No. 16,
mailed February 6, 1998) for the examiner's complete reasoning
in support of the rejections, and to appellant's Brief (Paper
No. 15, filed December 17, 1997) for appellant's arguments
thereagainst.
OPINION
We have carefully considered the claims, the applied
prior art references, and the respective positions articulated
by appellant and the examiner. As a consequence of our
review, we will reverse the obviousness rejections of claims 1
through 3, 5 through 10, 12 through 16, and 18 through 21.
Appellant argues (Brief, pages 5-6) that Watanabe's zero
detector output is not simultaneously calculated as recited in
each of independent claims 1, 8, 14, 20, and 21. The examiner
responds (Answer, pages 4-5) that
the degree of "simultaneously calculated" is the
same in Watanabe's zero detector as it is in
appellant's zero detector. Appellant's Fig. 6
clearly shows that the zero detector output bits
<2:0> are generated before the zero detector output
bits <5:3> because the signals that select the <2:0>
3
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