Appeal No. 1999-0014
Application No. 08/748,123
bits are generated before the <5:3> bits, note
selection unit 212.
In other words, the examiner admits that Watanabe's zero
detector output is not simultaneously calculated and,
therefore, fails to meet the claim limitation. We also note
that contrary to the examiner's assertion, output bits <2:0>
and output bits <5:3> in appellant's Figure 6 do appear to be
calculated simultaneously, as they are output to a common
node, and bits <5:0> are output from the common node.
Accordingly, the examiner has failed to establish a prima
facie case of obviousness, and we cannot sustain the rejection
of claims 1 through 3, 5, 7 through 10, 12 through 16, and 18
through 21.
As to claim 6, the examiner combines Hannai with
Watanabe. However, claim 6 depends from claim 1, and,
therefore, includes the limitation above found lacking from
Watanabe that the zero detector output must be simultaneously
calculated. Hannai fails to cure this deficiency.
Consequently, we cannot sustain the obviousness rejection of
claim 6.
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