Ex parte LIEN - Page 1




          The opinion in support of the decision being entered today was not written for
                   publication and is not binding precedent of the Board.              

                                                             Paper No. 24              


                      UNITED STATES PATENT AND TRADEMARK OFFICE                        
                                    _____________                                      
                          BEFORE THE BOARD OF PATENT APPEALS                           
                                  AND INTERFERENCES                                    
                                    _____________                                      
                               Ex parte CHUEN-DER LIEN                                 
                                    _____________                                      
                                 Appeal No. 1999-0866                                  
                              Application No. 08/742,704                               
                                    ______________                                     
                                      ON BRIEF                                         
                                   _______________                                     

          Before THOMAS, KRASS, and GROSS, Administrative Patent Judges.               
          THOMAS, Administrative Patent Judge.                                         

                                  DECISION ON APPEAL                                   
               Appellant has appealed to the Board from the examiner's                 
          final rejection of claims 12 through 23, 35 through 38 and 55.               
          Representative claim 12 is reproduced below:                                 
                    12.  A process for forming an interconnect                         
               structure, comprising the steps of:                                     
                    depositing a first conductive layer overlying one                  
               surface of a semiconductor substrate;                                   
                    forming a first dielectric layer overlying said                    
               first conductive layer;                                                 





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