Appeal No. 1999-0866
Application No. 08/742,704
forming a via in said first dielectric layer;
forming a first conductive plug within said via; and
selectively removing a first portion of said first
conductive plug, a first portion of said first dielectric
layer and a first portion of said first conductive layer
thereby forming said interconnect structure, said
interconnect structure comprising a first conductive lead
formed by a second portion of said first conductive
layer, a second conductive plug formed by a second
portion of said first conductive plug and a second
dielectric layer formed by a second portion of said first
dielectric layer wherein said second conductive plug has
an upper surface, a lower surface contacting an upper
surface of said first conductive lead, a first side
aligned with a side of said first conductive lead, a
second side in contact with said second dielectric layer
and a third side in contact with said second dielectric
layer, said second side and said third side being
adjacent to one another.
The following references are relied on by the examiner:
Brighton et al. (Brighton) 4,996,133 Feb. 26,
1991
Ozaki et al. (Ozaki) 5,084,416 Jan. 28,
1992
Ohshima 5,420,074 May 30,
1995
(filed Sep. 08,
1994)
Wolf, “Multilevel-Interconnect Technology For VLSI and ULSI,”
Silicon Processing For The VLSI ERA - Volume II: Process
Integration, pp. 222-23, 253 (Sunset Beach, CA, Lattice Press,
1990).
Claims 12 through 23, 35 through 38 and 55 stand rejected
under 35 U.S.C. § 103. As evidence of obviousness, the
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