Appeal No. 1999-0886
Application No. 08/722,738
Reference is made to the briefs and answer for the respective positions of
appellants and the examiner.
OPINION
In rejecting claims 1 and 4, the examiner identifies Nakamura as disclosing an
EPROM with FETs Tr1-Tr8, having source/drain regions 5 and capacitors FC1-FC8
coupled to gates 8. The examiner recognizes that Nakamura does not disclose the LDD
structure of the instant claimed invention but relies on Figures 1 and 8 and the abstract of
Momi for the suggestion to use an LDD structure, including a source and drain region,
lightly doped regions, heavily doped regions, gate electrode and a channel region, to
eliminate the injection of hot electrons into the gate oxide and stop soft leak. The examiner
then concludes that it would have been obvious to incorporate the LDD structure of Momi
into Nakamura’s device “to eliminate the injection of hot electrons into the gate oxide and
stop soft leak” [answer-page 3].
Appellants contend that Nakamura stores information using the polarization of the
ferroelectric capacitor and does not store charge generated in the channel region in
response to a logic state programming voltage applied between one of the source and
drain regions and the gate electrode. Contrary to Nakamura, the instant claimed
4
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