Appeal No. 1999-1630
Application No. 08/784,775
logic (CML) level signal to a MOS level signal. This is said to permit a level conversion circuit which
operates at high speed even at a low power-supply voltage.
Representative independent claim 1 is reproduced as follows:
1. A level conversion circuit comprising:
a first bipolar transistor having a base supplied with a first reference voltage;
a first resistor having a first end connected to a first potential line and a second end connected
to the emitter of said first bipolar transistor;
a second resistor having a first end connected to a second potential line and a second end;
a third resistor having a first end connected to said second potential line and a second end;
a first MOS transistor of a first channel type having a gate coupled to an input terminal, a
source coupled to the collector of said first bipolar transistor and a drain coupled to the second end of
said second resistor;
a second MOS transistor of said first channel type having a gate supplied with a second
reference voltage, a source coupled to the collector of said first bipolar transistor and a drain coupled
to the second end of said third resistor;
a third MOS transistor of a second channel type having a gate directly connected to the drain of
said first MOS transistor, a source coupled to said second potential line and a drain;
a fourth MOS transistor of said second channel type having a gate directly connected to the
drain of said second MOS transistor, a source coupled to said second potential line and a drain;
a fifth MOS transistor of said first channel type having a gate coupled to the drain of said fourth
MOS transistor, a drain coupled to the drain of said fourth MOS transistor and a source coupled to a
third potential line;
a sixth MOS transistor of said first channel type having a gate coupled to the gate of said fifth
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