Appeal No. 1999-1630
Application No. 08/784,775
MOS transistor, a drain coupled to the drain of said third MOS transistor and a source coupled to said
third potential line; and
an output terminal coupled to the drain of said third MOS transistor.
The examiner relies on the following reference:
Nagasawa 5,304,870 Apr. 19, 1994
The examiner also relies on admitted prior art [APA] depicted in Figure 2 of the instant application.
Claims 1-6 stand rejected under 35 U.S.C. 103 over APA in view of Nagasawa.
Reference is made to the briefs and answer for the respective positions of appellant and the
examiner.
OPINION
In accordance with appellant’s grouping of the claims, at page 4 of the principal brief, claims 1, 4
and 6 will stand or fall together while each of claims 2, 3 and 5 will stand or fall on its own.
It is the examiner’s position that APA discloses the claimed invention but for the first and second
MOS transistors of a first channel type as called for in claim 1. The examiner cites Nagasawa (Figure 1
and column 1, lines 32-35) for a level shifter circuit that comprises MOS transistors (Q1-Q2) for the
purpose of reducing power consumption. The examiner concludes that it would have been obvious to
incorporate the MOS transistors taught by Nagasawa into APA, by replacing transistors Q2-Q3 of
APA with the MOS transistors of Nagasawa for the purpose of reducing power consumption.
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