Appeal No. 1999-1631
Application 08/733,586
action, is explained in the Answer (at 4-7), to which
appellant responded with a Reply Brief.
The examiner relies on Figures 2a and 4 of Harari.
Figure 4 is a plan view of the latch circuit depicted in
schematic form in Figure 2a (col. 5, ll. 42-44). As is
apparent from the schematic, a p-channel transistor Q and an
1
n-channel transistor Q form a first inverter that is cross-
2
coupled to a second inverter formed of a p-channel transistor
Q and an n-channel transistor Q . As is also apparent from5
3 4
the symbols in Figure 2a, the n-channel transistors Q and Q 2 4
are of the floating gate type. Figure 4 includes dashed
rectangles surrounding each of the symbols Q -Q . Dashed
1 6
rectangles 73 and 75, which surround symbols Q and Q , are 2 4
described as representing the floating gates of those
transistors (col. 15, l. 17), as is also apparent from Figure
5Appellant does not deny that the p-channel and n-
channel transistors are pull-up and pull-down transistors,
respectively, as required by claim 1.
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