Appeal No. 1999-1631
Application 08/733,586
horizontally to the left of the gate of the first n-channel
transistor (Q ) and that the gate of the second p-channel
2
transistor (Q ) is offset horizontally to the left of the gate
3
of the second n-channel transistor (Q ), thereby satisfying
4
claims 1's requirement that these two offsets be in the same
horizontal direction. Appellant's argument (Reply Brief at 3)
that Harari's discussion of Figures 4 and 4a at column 14,
line 48 to column 15, line 25 does not contain "a remote hint
of gate offset of any type, let alone the offset as claimed in
claim 1" is unpersuasive, as a rejection for anticipation may
be based on a feature that is shown in the drawings but not
discussed in the specification. See In re van Deventer, 223
F.2d 274, 276, 106 USPQ 121, 123 (CCPA 1955) ("It is quite
true that an incidental, or even an accidental, showing may
constitute an anticipation and, accordingly, if claim 19 were
readable on the drawing of the French patent, it would be
immaterial that the taper of the passage is not specifically
described.").
Regarding the requirement of claim 1 that the n-channel
transistors be "laterally aligned," the examiner argues that
transistors Q and Q are laterally aligned because "a line2 4
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