Appeal No. 1999-2258
Application No. 08/431,720
receives data from either the main memory or the video memory
and performs a graphics operation on the data, and a memory
controller that controls the memory subsystem so that at one
time the datapath circuit receives the data from the main
memory and at another time the datapath circuit receives the
data from the video memory.
Claim 1 is the only independent claim on appeal, and it
reads as follows:
1. For use in a computer system having a data
processor, a system bus, and a memory subsystem
comprising main memory and video memory, a hardware
graphics accelerator comprising:
a datapath circuit connected to the system bus
and to the memory subsystem for receiving data from
the memory subsystem, performing a graphics
operation upon the data, and returning the data to
the memory subsystem; and
a memory controller connected to the system bus,
to the datapath circuit, and to the memory subsystem
for controlling the memory subsystem such that at
one time the datapath circuit receives the data from
the main memory and at another time the datapath
circuit receives the data from the video memory.
The reference relied on by the examiner is:
Lehman et al. (Lehman) 5,450,542 Sep. 12, 1995
(filed Nov. 30,
1993)
Claims 1 through 14 stand rejected under 35 U.S.C. §
2
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