Appeal No. 1999-2258
Application No. 08/431,720
subsystem such that at one time the datapath circuit
receives the data from the video memory (see col[s.]
5-6, lines 10-65 and figures 3, 5).
Appellants argue (brief, page 7) that:
Lehman discloses two separate paths and two
distinct address ranges for each of the graphics and
main memory accesses. As a result, Lehman’s
graphics circuitry (e.g.[,] ACCEL 414, PIXEL LOGIC
416, etc.) has no access to main memory data since
as can be seen in Figure 4, graphics data, having a
particular address range, is only routed through the
graphics circuitry portion of controller 400 between
bus 405 and the memory interface 408. Main memory
data, having a different address range than the
video data, passes through a separate route from
memory interface 408 to
bus interface 500 on bus 407 and bypasses the graphics
circuitry. As a result, Lehman’s graphics circuitry
cannot perform any graphics operations on data from main
memory.
In response to the examiner’s statement (answer, page 6) that
the shared memory 304 (Figure 3) “can be concurrently used,
and dynamically reconfigured for both graphics and system
function[s] as claimed,” appellants argue (reply brief, page
3) that “[r]egardless of how the memory is configured, shared,
or concurrently used, the graphics data and system data still
follow their exclusive paths dictated by Lehman’s underlying
architectural structure and function (column 5, lines 15-26)
and Lehman’s clear division in address ranges between the
5
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