Appeal No. 1999-2258
Application No. 08/431,720
Reference is made to the briefs (paper numbers 15 and 17)
and the answer (paper number 16) for the respective positions
of the appellants and the examiner.
OPINION
We have carefully considered the entire record before us,
and we will reverse the 35 U.S.C. § 102(e) rejection of claims
1 through 14.
To anticipate a claim, a prior art reference must
disclose every limitation of the claimed invention, either
explicitly or inherently. See Glaxo Inc. v. Novopharm Ltd.,
52 F.3d 1043, 1047, 34 USPQ2d 1565, 1567 (Fed. Cir.), cert.
denied, 516 U.S. 3378 (1995). The examiner’s rejection of
claim 1 is as follows (answer, pages 3 and 4):
Regarding claim 1, Lehman et al.’s BUS INTERFACE
WITH GRAPHICS AND SYSTEM PATHS FOR AN INTEGRATED
MEMORY SYSTEM discloses a computer system having a
data processor 302, “a system bus 500”, and “a
memory subsystem bus 408” comprising main memory and
video memory 114, a hardware graphics accelerator
comprising a “data path circuit 407 connected to the
system bus to the memory and to the memory
subsystem”, as in fig[.] 4; for receiving data from
the memory subsystem, performing a graphics
operation upon the data, and returning to the memory
subsystem (see col[.] 8, lines 18-40 and figure 4);
and a memory controller 316 connect[ed] to the
system bus, to the datapath circuit, and to the
memory subsystem for controlling the memory
4
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