Appeal No. 1999-2398
Application No. 08/825,427
(brief, page 8). Appellants argue (brief, pages 5 and 6)
that:
Matsuo discloses an instruction decoding unit
coupled to an address calculation unit and a data
operation unit. See Fig. 26. However, Appellants
respectfully submit that simply disclosing a single
instruction unit coupled to multiple functional
units does not teach or suggest creating multiple
instruction entities based on an original
instruction where the multiple instruction entities
are executed independent of each other. Multiple
functional units with a single instruction unit is
[sic, are] known for use with pipelined
architectures. The stages of the pipeline are
performed in a specific order for each instruction.
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