Appeal No. 1999-2702
Application No. 08/509,867
BACKGROUND
The appellant's invention relates to a processor for performing subword
permutations and combinations. An understanding of the invention can be derived from a
reading of exemplary claim 1, which is reproduced below.
1. An apparatus for generating permutations of an input data word, said
apparatus comprising:
an input register for holding said input data word;
means for partitioning said input register into a plurality of sub-words,
each said sub-word being characterized by a location in said input register
and a length greater than one bit;
an output register for holding said permutations of said input data
word, said output register being different from said input register; and
means, responsive to an instruction, for directing at least one of said
sub-words to a location in said output register that differs from said location
occupied by said sub-word in said input register, said location being
specified by said instruction, the ordering of said sub-words in said output
register differing from the order obtainable by a single shift or rotation of the
contents of said input register or by a rotation of the contents of said input
register with one path from said input register to said output register being
disabled, the ordering of said sub-words in said output register being
independent of the contents of said sub-words.
The prior art reference of record relied upon by the examiner in rejecting the
appealed claims is:
Phillips et al. (Phillips) 5,471,628 Nov. 28, 1995
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