Ex parte LEE - Page 5




              Appeal No. 1999-2702                                                                                        
              Application No. 08/509,867                                                                                  


              35 U.S.C. § 102, we interpret the examiner's position to be that Phillips has the basic                     
              teachings upon which a skilled artisan would have been able to practice or suggest the                      
              claimed invention.  This is not the standard upon which to evaluate a rejection for                         
              anticipation.  Appellant argues that Phillips does not disclose a system which can generate                 
              “all” permutations because they are not required and Phillips teaches minimizing the                        
              hardware to only those needed to support the required mask instructions.  (See reply brief                  
              at page 2 and Phillips at columns 16-17).  We agree with appellant that the level of                        
              disclosure in Phillips does not teach the invention as required under 35 U.S.C. § 102 since                 
              Phillips does not clearly teach other than the cyclic permutation.  While the specification                 
              and claims of Phillips appear to mention “any permutation” (Phillips at columns 24) and                     
              non-cyclic permutations with respect to the “gather” and "spread" functions of the IBM 370                  
              mainframe computer (Phillips at columns 25), Phillips does not in itself or by inherency                    
              teach the invention as recited in claim 1 with respect to the following limitations:                        
                     means, responsive to an instruction, for directing at least one of said                              
                     sub-words to a location in said output register that differs from said location                      
                     occupied by said sub-word in said input register, said location being                                
                     specified by said instruction, the ordering of said sub-words in said output                         
                     register differing from the order obtainable by a single shift or rotation of the                    
                     contents of said input register or by a rotation of the contents of said input                       
                     register with one path from said input register to said output register being                        
                     disabled, the ordering of said sub-words in said output register being                               
                     independent of the contents of said sub-words.                                                       




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