Appeal No. 2000-0160
Application 08/595,150
BACKGROUND
The invention relates to an integrated circuit and a method
of fabricating an integrated circuit. The disclosed invention is
described in Appellant's brief, pages 3-4.
Claim 19 is reproduced below.
19. An integrated circuit having a plurality of
semiconductor devices therein and a multilevel metallization
structure for interconnection of said semiconductor devices
thereon, said multilevel metallization structure comprising,
a plurality of substantially parallel, separated,
patterned metal layers, each said metal layer being
separated by an interlevel dielectric (ILD) layer of silicon
dioxide therebetween, said patterned metal layers being
comprised of electrically conducting lines, said
electrically conducting lines having top surfaces and edge
surfaces;
said interlevel dielectric layers between said metal
layers having vias therethrough, each said via having via
sidewalls 55 and a via bottom end surface 57, wherein at
least one of said vias has a first portion of said via
bottom end surface 57 being contiguous with a portion of
said top surface of one of said electrically conducting
lines and a second portion of said via bottom end surface 57
being above a portion of said edge surface of said one of
said electrically conducting lines, said one via thereby
being misaligned with respect to said one of said
electrically conducting lines, said vias having conducting
via plugs therein, said via plugs providing electrical
connectivity between said metal layers;
one or more of said metal layers having an insulating
ILD via etch stop cap layer contiguously thereon, said etch
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007