Appeal No. 2000-0452
Application No. 08/622,389
absent Appellant’s teaching regarding the control of power
consumption and operation speed of the logic circuit” (brief at
pages 6 and 7).
The examiner asserts (answer at page 4) that “it would have
been obvious . . . to employ the teaching of Tomisawa to control
the delay time of other logic circuits . . . so that the control
of all the transistors on the same substrate could be uniform and
[all the transistors] are subject to similar process variations,
thus, the delay time for all the logic circuits could be
controlled similarly.” The examiner further asserts in response
to the lack-of-motivation argument (answer at page 9) that “the
combination is based on the teachings of Tomisawa and Kamisaka to
control the delay time of other logic circuits in a similar
manner as the oscillator of Tomisawa and the delay of Kamisaka
are controlled.”
In providing motivation or a suggestion to combine, we note
that the Federal Circuit states, in In re Lee, 277 F.3d 1338,
1342-43, 61 USPQ2d 1430, 1433 (Fed. Cir. 2002),
[t]he essential factual evidence on the issue of
obviousness is set forth in Graham v. John Deere Co.,
383 U.S. 1, 17-18, 148 USPQ 459, 467 (1966) and
extensive ensuing precedent. The patent examination
process centers on prior art and the analysis thereof.
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