Appeal No. 2000-0975
Application No. 08/956,402
graphic objects that are generated by a main processor and passed to a graphics
processor, as described by Gauthier at columns 6 and 7 and shown in Figure 3 (queue
38 associated with graphics processor 18).
With respect to claim 2, we note that the “tasks” which are to be performed by
the at least one of the parallel processors are not specified. The claim thus embraces
geometry processing and rasterization that may be performed by a parallel processor
while the main processor is performing language interpretation tasks. Gauthier at
column 9, lines 13 through 19 reveals that the main processor (MPU) may be
interpreting a second page while a graphics processor (GPU) is rendering bitmaps and
dispatching bands for the first page. We therefore sustain the rejection of claim 2.
We also sustain the rejection of claim 3. Molnar, at pages 24 and 25, reveals
that tasks may be sorted or redistributed for optimal use of the parallel processors. The
artisan would have considered it obvious that some parallel processors perform tasks
(e.g., geometry processing) for a “current page” while other of the parallel processors
perform tasks (e.g., rasterization) for a “previous page.”
We sustain the rejection of claims 4 and 5. Molnar teaches a sort-first and a
sort-middle scheme (e.g., pages 24 and 25).
We sustain the rejection of claim 6. Guttag discloses a single-chip architecture
with four parallel processors and a master processor (p. 60, Fig. 4).
Instant claim 7 recites “wherein said main processor is on a separate chip.” We
agree with the examiner that the distinct functions as shown in the block diagram of
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