Appeal No. 2000-1204
Application No. 08/786,818
Claim 1 is illustrative of the claimed invention, and it
reads as follows:
1. A configurable logic block (CLB) for use in a field
programmable gate array, the CLB comprising:
a plurality of input lines;
a carry-in line;
a carry-out line;
at least one lookup table, each such lookup table
receiving input signals from N of the plurality
of input lines and having an output line;
a dedicated AND gate receiving two input signals
from two of the plurality of input lines; and
a carry chain having a carry input coupled to the
carry-in line and a carry output coupled to the
carry-out line, and at least one carry
multiplexer controlled by the lookup table
output line, each such multiplexer having at
least two inputs, one such input being provided
by the carry-in line, and the other such input
being provided by the AND gate.
The references relied on by the examiner are:
New et al. (New) 5,481,206 Jan. 2,
1996
Rose et al. (Rose) 5,724,276 Mar. 3,
1998
(filed Jun. 17,
1996)
Claims 1 and 3 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Rose.
3
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