Appeal No. 2000-1204
Application No. 08/786,818
Claims 4 and 7 through 10 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Rose in view of New.
Reference is made to the briefs (paper numbers 15 and 17)
and the answer (paper number 16) for the respective positions
of the appellants and the examiner.
OPINION
We have carefully considered the entire record before us,
and we will reverse the obviousness rejection of claims 1, 3,
4 and 7 through 10.
The examiner’s rejection is as follows:
As per claim 1, Rose et al[.] discloses in Fig.
4a a configurable logic block (CLB) for use in a
field programmable gate array (FPGA). The CLB
clearly has a plurality of input lines, a carry-in
line, a carry-out line, at least one lookup table
(LUT F), and a carry chain having a carry input
coupled to the carry-in line and a carry output
coupled to the carry-out line. The carry chain also
has at least one carry multiplexer (CMUX) controlled
by the output of the lookup table and having one
input being provided with the carry- in line and
another input being provided with an AND logic of 2
input lines (a0b1) which are also the input lines to
the lookup table. It [is] noted that Rose et al.
discloses the AND logic being provided by another
lookup table (LUT G), whereas, in the present
invention the AND logic [is] being provided by a
dedicated AND gate. However, in the field of FPGA,
the use of a lookup table and the use of a gate to
provide a logic function are both well known and are
art recognized equivalents with a trade off between
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