Appeal No. 2001-2351
Application No. 08/772,443
The Prior Art
In Figure 3 of Parks, a caching disk controller 304 is
provided which includes a bus bridge 320 that forms an interface
between a memory 324 of the disk controller and a host computer
302, 303. The caching disk controller 304 further includes SCSI
processor 328, 330 for controlling the transfer of data from a
SCSI disk drive 306 to the memory 324 via a local bus 326. A
zero latency DMA controller 408 (Figure 4) embodied within the
bus bridge snoops the local bus 326 as data is being transferred
from the SCSI disk drive to the memory 324, and thereby allows
the data to be sequentially latched within a data FIFO 504
(Figure 5) of the bus bridge concurrently with its transfer into
the memory. As a result, the requested data may be provided from
the bus bridge to the host computer with reduced delay, while the
data continues to be stored within the memory 324 to accommodate
high hit rates during subsequent transfers.
The Rejection under 35 U.S.C. § 102(e)
Independent Claims 1, 4, 9, 20 and 31
Appellants argue that local memory 324 in Figure 3 of Parks
is a cache memory, which is not the same as a data buffer.
Purportedly, a buffer is not interchangeable with a cache because
the functionality of the two devices are different. It is urged
-4–
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