Appeal No. 1999-0166
Application No. 08/656,544
system clock signal during normal operation and the test clock
signal during loading of program instructions during a test
operation. During a test operation, the clock selecting
circuitry is responsive to one or more clock selecting bits
within a program instruction to select either the test clock
signal or the system clock signal to drive the processor core
to execute the program instruction.
Claim 1 is illustrative of the invention and reads as
follows:
1. Apparatus for processing data, said apparatus
comprising:
(i) a processor core operable under control of
program instructions;
(ii) a clock circuit for supplying a system clock
signal to said processor core;
(iii) a test clock circuit for supplying a test
clock signal to said processor core;
(iv) a clock selector for selecting which one of
said system clock signal and said test clock signal
drives operation of said processor core; and
(v) an auxiliary circuit coupled to said processor
core and driven by said system clock signal irrespective
of which clock signal is selected for supply to said
processor core by said clock selector, said auxiliary
circuit being accessed by said processor core only when
executing a program instruction from a subset of said
program instructions;
2
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