Ex Parte BLALOCK et al - Page 12




          Appeal No. 1999-2347                                                        
          Application 08/892,560                                                      

          etch step of their claim 21 is not anticipated or rendered                  
          obvious by Woo.  Thus, going one way, Appellants claim "the same            
          patentable invention" as Woo.                                               
               In any event, the question under 37 CFR §§ 1.131 and                   
          1.601(n) is whether Woo is anticipated or rendered obvious if               
          Appellants' claim 21 is considered to be prior art.  Neither the            
          Examiner nor Appellants address this question.                              
               We conclude that Woo's claim 1 would have been obvious over            
          Appellants' claim 21 taken together with Wolf, Silicon Processing           
          for the VLSI Era ) Volume 2: Process Integration  (Lattice Press            
          1990), pp. 280-281, 294 (copy attached).  Woo's claim 1 is                  
          directed to the right-hand structure of Woo's Fig. 12.  We                  
          address what we consider to be arguable differences.  One                   
          difference is that Woo's claim 1 recites that the first conductor           
          is on a "dielectric layer," whereas Appellants' claim 21 recites            
          a "substrate."  It can not be reasonably contested that it was              
          known to make a substrate from a dielectric layer.                          
               Another difference between Woo's claim 1 and Appellants'               
          claim 21 is that Woo's claim 1 recites that the first conductor             
          is "overlying and abutting a metal plug in a first dielectric               
          layer" whereas Appellants' claim 21 does not call for a metal               
          plug.  We find that it was well known in the semiconductor art to           
          deposit conductive lines over metal plugs to provide multilayer             
          interconnects.  Also, Wolf, Fig. 4-59(d), shows two metal                   

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