Appeal No. 2001-0513
Application No. 09/096,550
(Answer, pages 10-11) that the VLD and RLD do not read and write
data from the local memory at the same rate. However, as pointed
out by appellants (Brief, page 15) in Artieri, the write
operations of the VLD can be interrupted by the RLD when the
latter can no longer receive data to be processed. Therefore,
the VLD and RLD of Artieri are dependent upon each other, which
means that their respective reading and writing rates must be
dependent upon each other.
The examiner (Answer, page 10) also points to column 3,
lines 38-43, wherein Artieri states that the system includes "a
memory bus controlled by a memory controller to exchange data
between the processing elements at rates adapted to the
processing rates of these elements." The examiner contends that
this passage indicates that the processing rates are independent
of each other. However, although Artieri mentions processing
rates, nothing in the reproduced passage suggests that the
processing rates must be independent of each other. As we find
no teaching or suggestion in Artieri of independent rates of
writing and reading from non-local memory by elements of the
system, Artieri fails to disclose each and every element of the
claims. Accordingly, Artieri cannot anticipate the claims, and
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