Appeal No. 2001-0571 Page 2
Application No. 09/026,790
1. A method of generating synthesis scripts to synthesize
integrated circuit (IC) designs from a generic netlist
description into gate-level description, said method comprising
the steps of:
identifying hardware elements in the generic netlist;
determining key pins for each of said identified hardware
elements;
extracting design structure and hierarchy from the Generic
netlist;
generating script to cause a logic synthesis tool to apply
bottom-up synthesis to modules and sub-modules of the IC design;
generating script to cause a logic synthesis tool to apply
top-down characterization to modules and sub-modules of the IC
design; and
generating script to cause a logic synthesis tool to repeat
said bottom-up and said top-down applications until constraints
are satisfied.
The prior art reference of record relied upon by the
examiner in rejecting the appealed claims is:
Gupte et al (Gupte) 5,812,416 September 22, 1998
(filed July 18, 1996)
Claims 1-6 and 9-20 stand rejected under 35 U.S.C. § 102(e)
as being anticipated by Gupte. Rather than reiterate the
conflicting viewpoints advanced by the examiner and appellant
regarding the above-noted rejection, we make reference to the
examiner's answer (Paper No. 11, mailed October 3, 2000) for the
examiner's complete reasoning in support of the rejection, and to
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