Appeal No. 2001-0571 Page 6
Application No. 09/026,790
Although we agree with the examiner (answer, page 13) that
appellant's specification refers to generic netlists as a netlist
that is created from the RTL code that has not yet been
correlated with a technology specific library of cells, we agree
with appellant (brief, page 3) that synthesis tools typically
generate a generic netlist as an intermediate step to producing a
final technology-dependent netlist from the input HDL code, and
that analysis of the generic netlist will identify many design
issues that are missed when only analyzing HDL code. We find
support for appellant's assertions in figures 12, 13, and 36,
which explain the process for analyzing and elaborating on the
input RTL code in HDL format, to produce a generic netlist,
remove it from compiler 352 as a dump file, and then analyzing
the generic netlist in the process of creating the gate level
technology-specific netlist. Although Gupte discloses (col. 4,
lines 56-61) that during the design phase, arbitrary HDL code is
transformed into Synthesizable Behavioral HDL code, we find no
teaching or suggestion in Gupte that arbitrary HDL code is a
generic netlist. We are cognizant of the disclosure of Gupte
(col. 7, lines 36-39) that an I/O netlist is generated at the
chip level at step 218, and that the I/O netlist may be used to
simulate the application specific ICs. However, we find no
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