Appeal No. 2001-1189
Application No. 08/824,140
1. A dynamic logic circuit operable for reset during a
precharge clock phase and to evaluate during an evaluate
clock phase comprising:
first and second NFETs coupled in series between a
first node and a first reference voltage, wherein gate
electrodes of said first and second NFETs are operable for
receiving a data input;
a first PFET coupled between a second reference voltage
and a second node coupling said first and second NFETs,
wherein a gate electrode of said first PFET is operable for
receiving said data input, so that said first and second
NFETs and first PFET reduce susceptibility to erroneous
discharge of said first node during said evaluate phase;
and
a third NFET coupled between said second NFET and said
first reference voltage, wherein said third NFET is operable
for receiving a clock signal.
The references relied on by the examiner are:
Lyon 5,440,243 Aug. 8, 1995
D’Souza et al. (D’Souza) 5,546,022 Aug. 13, 1996
Claims 1, 2, 4 through 10, 12 through 181 and 20 through 27
stand rejected under 35 U.S.C. § 103(a) as being unpatentable
over Lyon in view of D’Souza.
1 If claims 17 and 18 are supposed to be read on the Figure
6 embodiment of a multiplexer circuit, then we question the
written description and the definiteness of the claim
17 and claim 18 limitation of “third and fourth NFETs coupled in
series between said first node and said first reference voltage,
wherein gate electrodes of said third and fourth NFETs are
operable for receiving a second data input.” This claim
limitation cannot be read on such a multiplexer circuit.
2
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