Appeal No. 2001-1419
Application No. 09/199,960
implanting into the substrate at a second energy level
a second concentration of a second dopant species, whereby
source and drain regions are formed in the substrate and
aligned with the alignment structure;
growing an epitaxial layer on the substrate adjacent to
the spacers;
removing the polysilicon alignment structure, thereby
forming a trench between the spacers;
forming a gate dielectric in the trench;
forming a silicide layer on the epitaxial layer; and
forming a metal gate electrode in the trench, wherein
the top of the gate electrode is disposed only over the
lightly doped drain regions.
The Examiner relies on the following prior art:
Rodder et al. (Rodder) 5,198,378 Mar. 30, 1993
Stanley Wolf (Wolf), Silicon Processing for the VLSI Era, pp.
144-51, 157-58 (Lattice Press, Sunset Beach, CA 1990).
A. Chatterjee et al. (Chatterjee), “Sub-100 nm gate length metal
gate NMOS transistors fabricated by a replacement gate process,”
International Electron Devices Meeting, 1997. Technical Digest.,
Int’l, pp. 33.1.1-33.1.4 (Dec. 1997).
Claims 9-17 stand finally rejected under 35 U.S.C. § 103(a)
as being unpatentable over Chatterjee in view of Rodder and Wolf.
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