Appeal No. 2001-1419
Application No. 09/199,960
prima facie case of obviousness. Initially, Appellants contend
(Brief, page 4; Reply Brief, pages 2 and 3) that the Examiner has
misinterpreted the Chatterjee reference as disclosing a gate
electrode that does not extend past the LDD (lightly doped drain)
regions or, in the words of claim 9, “ . . . wherein the top of
the gate electrode is disposed only over the lightly doped drain
regions.”
After careful review of the applied prior art references in
light of the arguments of record, we are in general agreement
with the Examiner’s analysis and position as stated in the final
Office action and the Answer. As asserted by the Examiner, the
pictures of an actual semiconductor device which make up Figure
2 of Chatterjee show at least the right side of the gate
electrode extending not quite as far as the edge of the spacer.
Further, although Chatterjee is silent about the fabrication
processing for forming the LDD regions, it is apparent to us from
the evidence of record, including Appellants’ own arguments
(Brief, page 4), that the conventional manner of forming
semiconductor gate and source/drain regions is to initially form
LDD regions, aligned with an alignment structure, in a substrate.
Sidewall spacers aligned with the alignment structure are then
formed over the LDD regions which act as a mask for the
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