Appeal No. 2001-1550
Application 09/105,830
See page 11 of Appellants’ specification. Figure 8f shows
depositing a thin adhesion-promoting layer 824 of Ti-Al-N
followed by a bottom electrode layer 826 of platinum. See page
12 of Appellants’ specification. Figure 8k shows depositing a
capacitor dielectric layer 836 and then depositing a platinum top
electrode field plate 838. See page 14 of Appellants’
specification.
Independent claim 1 is reproduced as follows:
1. A memory circuit, including a memory cell comprising:
(a) a capacitor including:
a bottom electrode having a conductive adhesion-
promoting layer at a first surface;
a storage layer in contact with a second surface of
said bottom electrode;
a top electrode in contact with said storage layer;
(b) a transistor comprising first and second terminals and a
wordline control terminal; and
(c) a bitline coupled to said first transistor terminal;
said bottom electrode coupled to said second transistor
terminal by a plug comprising a barrier adjacent said adhesion-
promoting layer, said barrier being thicker than said adhesion-
promoting layer.
References
The references relied on by the Examiner are as follows:
Meikle et al. (Meikle) 5,231,306 Jul. 27, 1993
2
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