Appeal No. 2001-2089
Application 08/993,368
The claimed invention relates to a NAND-type flash
memory device having a core region which includes a stacked gate
flash memory structure. Further included in the stacked gate
flash memory structure is a conductive poly1 layer formed over a
tunnel oxide layer with an insulating layer overlying the poly1
layer and a conductive poly2 layer overlying the insulating
layer. The core region also includes a select gate transistor
which has a gate oxide layer formed with the same insulating
layer as the stacked gate flash memory structure and further
includes a poly2 gate layer formed over the gate oxide layer.
According to Appellant (specification, pages 3 and 4), by using,
as the gate oxide layer in the select gate transistor, the same
layer as the interpoly insulating layer in the stacked gate flash
memory structure, a dual core oxide manufacturing process is
eliminated, thereby producing a less expensive and more reliable
device.
Claim 17 is illustrative of the invention and reads as
follows:
17. A NAND-type flash memory device comprising:
a core region comprising a stacked gate flash memory
cell structure having a thin oxide material forming a tunnel
oxide layer, a first conductive material forming a poly1 layer
overlying the tunnel oxide layer, an insulating material forming
2
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