Appeal No. 2001-2089
Application 08/993,368
an insulating layer overlying the poly1 layer and a second
conductive material forming a poly2 layer overlying the
insulating layer; and
the core region further comprising a select gate
transistor having the same insulating layer used to form the
insulating layer in the stacked gate flash memory structure to
form a gate oxide layer, thus providing for the formation of the
insulating layer and the gate oxide layer in a single formation
step, and the second conductive material forming a gate layer
overlying the gate oxide layer.
The Examiner relies on the following prior art:
Maiti et al. (Maiti) 5,861,347 Jan. 19, 1999
(filed Jul. 03, 1997)
Komori et al. (Komori) 5,904,518 May 18, 1999
(filed Jun. 30, 1997)
Masaki Momodomi et al. (Momodomi), “A 4-Mb NAND EEPROM with Tight
Programmed Vt Distribution,” IEEE Journal of Solid-State
Circuits, Vol. 26, No. 4 (April 1991).
Claims 12-21, all of the appealed claims, stand finally
rejected under 35 U.S.C. § 103(a). As evidence of obviousness,
the Examiner offers Momodomi in view of Komori with respect to
claims 17, 18, and 20, and adds Maiti to the basic combination
with respect to claims 12-16, 19, and 21.
3
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 Next
Last modified: November 3, 2007