Appeal No. 2001-2477
Application No. 09/099,384
No references were relied on by the examiner in the rejection on appeal.
Claims 1, 2, and 4 through 24 stand rejected under the first paragraph of 35 U.S.C. § 112 for
lack of written description of the phrase “wherein said memory management system does not
internally duplicate the coherence state of the cache” (claim 1), and the phrase “determining if said
block exists in a dirty form in any other of the plurality of caches by directly probing those caches”
(claim 12).
Reference is made to the briefs (paper numbers 12 and 14) and the answer (paper number
13) for the respective positions of the appellants and the examiner.
OPINION
We have carefully considered the entire record before us, and we will sustain the lack of
written description rejection of claims 1, 2 and 4 through 11, and we will reverse the lack of written
description rejection of claims 12 through 24.
Appellants argue (brief, pages 6 through 9; reply brief, pages 1 through 4) that the prior art
(U.S. Patent No. 5,634,068 to Nishtala) discloses a memory management system (i.e., a system
controller 100) that uses “duplicate cache tags,” and that one of ordinary skill in the art would
recognize that their specification describes a system where the memory management system need
not maintain duplicate cache tags.
For an answer to both of appellants’ arguments, we turn to In re Wohnsiedler, 315 F.2d 934,
937, 137 USPQ 336, 339 (CCPA 1963) which states:
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