Appeal No. 2001-2638
Application 09/201,214
the examiner. This amendment cancelled claims 2-9 and 22-26.
Therefore, this appeal is directed to the rejection of claims 1,
21 and 27-30.
The disclosed invention pertains to a memory controller
for managing memory operations in a data processing system. One
particular aspect of the invention is the manner in which memory
requests from an input/output device to a data processor are
handled.
Representative claim 1 is reproduced as follows:
1. A method for managing memory operations in a data
processing system using a memory controller having a device bus
interface, a memory interface and a system bus interface, said
method comprising the steps of:
receiving a memory request from a device bus interface
at a memory controller having a store buffer;
responsive to receiving said memory request, satisfying
said memory request asynchronously with said memory request via a
transaction on one of said system bus interface or said memory
interface, utilizing said store buffer to schedule said
transaction by transferring a processor’s cache data to a device
coupled to said device bus by reading said processor’s cache data
posted in one or more arrays within said memory controller.
The examiner relies on the following references:
Abramson et al. (Abramson) 5,751,983 May 12, 1998
Panwar et al. (Panwar) 6,058,472 May 02, 2000
(filed June 25, 1997)
Kaiser et al. (Kaiser) EP 0 766 179 Apr. 02, 1997
2
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