Appeal No. 2001-2638
Application 09/201,214
With respect to representative claim 1, the examiner
cites Kaiser as teaching the claimed invention except that there
is no description in Kaiser of the store buffer which the
examiner has read on the “system read/write Q” and the “memory
read/write Q” of Kaiser. The examiner cites Panwar as teaching a
memory controller including a disambiguation buffer (MDB) that
has a store buffer. The examiner cites Abramson as teaching a
memory controller which has a store buffer. The examiner finds
that it would have been obvious to the artisan to replace the
system read/write Q and the memory read/write Q of Kaiser with
the MDB of Panwar which would allegedly result in the claimed
invention. The examiner also finds that it would have been
obvious to the artisan to operate the read/write Qs of Kaiser in
the same manner as Abramson operates the reservation stations
which would also allegedly result in the claimed invention
[answer, pages 4-6].
Appellants argue that the system read/write Q and the
memory read/write Q of Kaiser do not show or suggest a buffer
which may be utilized to schedule a memory request transaction in
the manner recited in independent claims 1 and 21. Appellants
also argue that neither Panwar nor Abramson teaches or suggests
the transfer of a processor’s cache that has been stored in a
6
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