Appeal No. 2001-2638
Application 09/201,214
memory controller to a device as set forth in the claimed
invention [brief, pages 6-9].
The examiner responds that the course of prosecution in
this application led to the obviousness issue hinging on the
“topology” of appellants’ invention. The examiner notes that
Kaiser was cited only to show this topology and that the
deficiencies of the read/write Qs of Kaiser are not relevant.
The examiner also responds that in a system where a single
controller connects all of the busses as in Kaiser, it clearly
follows that it would have been obvious to service load requests
from the device bus out of the store buffer since the memory
controller is directly connected to the device bus [answer, pages
7-8].
We will not sustain the examiner’s rejection. Although
the examiner suggests that we should draw certain inferences on
the question of obviousness based on the course of prosecution in
this case, we decline to do so. We must consider the claimed
invention and the clear teachings of the applied prior art.
Representative claim 1 recites that data which originated in a
processor’s cache is transferred to a device bus using the store
buffer of the memory controller. As noted by appellants, the
store buffer of Kaiser (the system and memory read/write Qs) is
7
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