Appeal No. 2002-0286
Application No. 09/113,995
simplified layout and routing with respect to certain signal
processing circuits.
Representative independent claim 19 is reproduced as
follows:
19. A cell library for use in designing integrated
circuits, comprising:
a cell which includes (1) a signal processing circuit; (2) a
buffer circuit for buffering a signal external to an integrated
circuit in which said cell is to be included; and (3) layout
information for specifying a layout of an interconnecting trace
between said signal processing circuit and said buffer circuit.
The examiner relies on the following references:
Smith et al. (Smith) 5,247,668 Sep. 21, 1993
Tanaka et al. (Tanaka) 5,737,237 Apr. 07, 1998
Kawakami 5,774,371 Jun. 30, 1998
Varadarajan et al. 5,838,583 Nov. 17, 1998
(Varadarajan) (filed Apr. 12, 1996)
Luk et al. (Luk) 5,883,814 Mar. 16, 1999
(filed Mar. 13, 1997)
Claims 1-30 stand rejected under 35 U.S.C. §102(e) as
anticipated by any one of Luk or Varadarajan or Tanaka or
Kawakami.
Claims 1-30 stand further rejected under 35 U.S.C. §102(b)
as anticipated by Smith.
Reference is made to the briefs and answer for the
respective positions of appellants and the examiner.
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