Appeal No. 2002-2309
Application No. 09/099,386
Claims 1 and 12 are illustrative of the claimed invention,
and they read as follows:
1. A system for managing access to caches connected to a
plurality of processors in a multiprocessor system, comprising:
a system port connectable to each of the plurality of
processors and configured to receive a request from a first one
of the processors, the request asking to modify a block of a
first cache of the caches, and the request corresponding to a
coherence state of the block of the first cache;
a memory manager connected to the system port and
configured, in response to the received request, (i) to direct
sending, over the system port, of probes to the caches, other
than the first cache, (ii) to receive cache state information,
over the system port, responsive to the probes, (iii) to
determine an acknowledgment based on the received cache state
information representing one of permission granted and permission
denied to modify the block of the first cache, and (iv) to direct
sending, over the system port, of the acknowledgment, to the
first one of the processors; and
wherein the memory manager does not internally duplicate a
coherence state of blocks of the caches.
12. A method of maintaining cache coherence in a
multiprocessor system having a plurality of caches and a main
memory, comprising the steps of:
sending a request to modify a block of a first cache of the
plurality of caches, the request corresponding to a coherence
state of the block of the first cache;
sending probes to the caches, other than the first cache, to
receive cache coherence state information responsive to the
probes, said probes each contain at least a data movement field
and a next state field;
determining an acknowledgment based on the received cache
coherence state information representing one of permission
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