Appeal No. 2002-2309
Application No. 09/099,386
Appellants argue (brief, pages 22 and 23) that:
The DTags of Nishtala are duplicate cache tags attached
to Nishtala’s system controller 110. See Nishtala’s
Figure 1. The fact that a duplicate cache tag needs
updating is not related to a next state field of a
probe command sent to caches of processors of a
multiprocessor system. For this reason alone
Applicants submit that the Examiner’s logic is flawed
and that the rejection should be reversed.
The figures relied upon by the Examiner, as well
as the corresponding portions of the specification do
not teach, suggest or even imply, alone or in
combination with Galles, that the probe command should
have both a data movement field and a next state field.
Nishtala discloses that the “System Controller 110
maintains a pending transaction status array 200 that
stores information on all pending and Active
transaction[s].” Nishtala, Col. 54, lines 6-8 . . . .
Clearly, Nishtala’s Transaction Status Array 200 is an
array residing within the System Controller 110. In
spite of this teaching, the Examiner relies upon
particular entries in the Status Array 200, DTag state
values 322 and S REPLY type 325, for a teaching [of] a
probe command having both a data movement field and a
next state field . . . . Nishtala, however, does not
teach, suggest or even imply that these two entries in
the array should be sent together within a probe
command to a processor. Further, since the DTags of
Nishtala are part of the system controller, why would
Nishtala teach that this entry should go anywhere
beyond the system controller?
We agree with the appellants’ arguments. Nothing in the
record supports the examiner’s contentions. For this reason, the
obviousness rejection of claims 12 through 23 is reversed.
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