Appeal No. 2003-0450
Application 09/394,039
claims 21, 25, and 29 have been indicated to be allowable
(examiner's answer, p. 9). Claims 5, 10, and 27 were amended by
amendment after final rejection (Paper No. 15) pursuant to the
examiner's recommendation (examiner's answer, Paper No. 19,
p. 9). Since the examiner noted that claim 5, and presumably
claim 10, would be allowable if amended (examiner's answer,
p. 9), we assume that the amendment overcomes the rejection of
claims 5 and 10 although the examiner makes no mention of this in
the communication (Paper No. 17) noting entry of the reply brief
and the amendment. Since the examiner only noted a problem with
the language of claim 27 and did not say that it would be allowed
if amended, we assume that claim 27 still stands rejected.
We reverse.
BACKGROUND
The disclosed invention relates to a semiconductor memory
device capable of performing a high speed read modify write
operation. Separate pins (or data buses) are provided for
reading data from memory and writing data to memory. An input
address is input to a read address decoding means to address the
memory for reading and is also input to an address delay means,
such as a first-in first-out (FIFO) buffer. The address is
delayed for a predetermined number of clock cycles and becomes
the write address which is decoded by a write address decoding
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