Appeal No. 2003-0450
Application 09/394,039
and that interpretation is not clear. Accordingly, the decoding
means limitations are not grounds for distinguishing over Kaneko.
Appellants also argue that Kaneko and Hyatt fail to disclose
"an address delay means by which said decoded write address
decoded by said write address decoding means is delayed by a
predetermined time from a read address decoded by said read
address decoding means, said predetermined time being set as a
predetermined plurality of times of basic synchronization pulse
periods so that the data read modify write operation is
accomplished in a pipeline manner by said basic synchronized
pulse," as recited in claim 2 (Br13-14).
The examiner finds that DR1 and DR2 correspond to the
claimed address delay means (EA6). The examiner states (EA6-7):
With regard to the final feature of claim 2, the
address delay means, Kaneko et al. appears to introduce the
delay to the operand data of a write request instead of the
address data (as required by the invention). In the end,
though, the result will be the same, since there is a
delayed write operation which occurs in response to the
passing of data through the delay register. In other words,
the request cannot be fully serviced until both operand data
and address data are received and delaying one or the other
will yield a similar result. Applicant simply chose to
delay the address data instead of the operand data.
Appellants argue that the examiner admits that Kaneko fails
to explicitly teach the claimed address delay means (RBr6). It
is argued that Kaneko fails to disclose delaying a decoded write
address decoded by the write address decoding means (RBr6). As
to the examiner's statement that delaying the address data will
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