Appeal No. 2003-0450
Application 09/394,039
Appellants argue that Kaneko and Hyatt fail to disclose
"a read address decoding means for independently decoding an
address of a read memory cell in response to a first designated
address" and "a write address decoding means for independently
decoding a write address of a memory cell in response to a second
designated address," as recited in claim 2 (Br13).
The examiner finds that either AD1 or AD2 is a read address
decoding means whenever a read address is directed to memory
matrix M1 or M2, respectively, and that either AD1 or AD2 is a
write address decoding means whenever a write address is directed
to memory matrix M1 or M2, respectively (EA5).
Appellants do not rebut the examiner's position in their
reply brief and, absent argument to the contrary, we consider the
examiner's finding to be reasonable. The limitations of "a read
address decoding means for independently decoding" and "a write
address decoding means for independently decoding" do not require
separate, dedicated read and write decoding means as disclosed in
Figs. 5 and 6, and do not preclude two decoding means that decode
both read and write addresses as shown in Kaneko. The term
"independently" is not defined in claim 2. While, perhaps, some
argument could be made that the limitation of a "read modify
write operation is accomplished in a pipeline manner" at the end
of claim 2 somehow implies separate read and write decoding means
which operate at the same time, this argument has not been made
- 5 -
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007