Appeal No. 2003-1690
Application 09/635,061
the conductive layer to form a gate dielectric (508; col. 30,
lines 1-4; figure 7E). Makita does not disclose the appellant’s
second gate dielectric layer.
Ipri discloses that in the prior art, when a monocrystalline
silicon island (116) was formed on a sapphire wafer (112), and
then a silicon dioxide gate dielectric layer (118) was formed on
the silicon island by thermal oxidation of the silicon island,
there was significant thinning (122, figure 1) of the silicon
dioxide layer at the boundary between the silicon island and the
wafer surface (114) (col. 2, lines 40-47). Ipri teaches that
this thinning degrades the dielectric strength of the gate
dielectric by about 67% (col. 2, lines 47-51).
One prior art approach disclosed by Ipri for overcoming this
problem was to deposit a polycrystalline silicon layer by
standard deposition techniques over a silicon island (216) and
the exposed substrate surface (214), and then completely
thermally oxidize the polycrystalline silicon layer to form a
silicon dioxide gate dielectric layer (218) (col. 2, line 64 -
col. 3, line 4). Ipri teaches that “[s]ince the structure of the
device 210 [formed by the second discussed prior art process]
does not incorporate the thin dielectric regions 122 of
device 110 [formed by the first discussed prior art process], it
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