Appeal No. 2003-1973
Application No. 09/192,952
a Fermi-FET channel in the integrated circuit
substrate, between the spaced apart source and drain
regions;
a gate insulating layer on the integrated circuit
substrate, between the spaced apart source and drain
regions; and
a gate electrode on the gate insulating layer,
wherein the gate electrode is closer to the source
region than to the drain region and wherein the
Fermi-FET is free of other electrodes between the
source and drain regions.
The examiner relies upon the following references as
evidence of obviousness:
Dennen 5,543,654 Aug. 06, 1996
Matsumoto et al. (Matsumoto) 5,599,741 Feb. 04, 1997
Mori, et al. (Mori) JP 11-317519 Nov. 16, 1999
(filed May 01, 1998)
Unagami, T. “High-Voltage Ply-Si TFT’s with Multichannel
Structure” IEEE Transactions on Electron Devices, Vol. 35,
no. 12 (December 1988), pp. 2363-2367.
Appellants’ claimed invention is directed to a Fermi-
threshold field effect transistor (Fermi-FET) comprising a gate
electrode and spaced apart source and drain regions wherein the
drain region is offset. According to appellant “[o]ffset drain
Fermi-Fets may be used, for example for high voltage and/or high
2
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