Ex Parte GOVER et al - Page 6




          Appeal No. 1999-0288                                                        
          Application No. 08/538,071                                 Page 6           


          this deficiency in Wibecan, the examiner turns to Brantley for a            
          teaching of monitoring events including the number of times a               
          specific address is accessed.  The examiner asserts (final                  
          rejection, page 3) that it would have been obvious to allow                 
          Wibecan's system to control the counting of events such as                  
          specific address references, as taught by Brantley because it               
          would allow Wibecan's system to measure the performance of                  
          accesses to specific addresses, which will give a user a chance             
          to adjust any parameters or configurations of the system in order           
          to receive better performance from the data processing system.              
               The examiner further asserts (final rejection, page 4) that            
          Wibecan does not show the use of the performance monitor bit                
          being located in a machine state register.  The examiner takes              
          the position (final rejection, page 4) that “it would have been             
          obvious to one of ordinary skill in the art to realize that the             
          enablement of a processing system to recognize which mode or                
          process it is operating in, such as user or supervisor mode, are            
          usually located in a register which is accessible to the                    
          processing systems other elements.  This ensures that certain               
          processes can not be executed while in certain modes” and that              
          (pages 4 and 5) “it would have found it obvious to place the                
          process recognition bit (flags etc.) in a state register which              







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