Appeal No. 1999-0288
Application No. 08/538,071 Page 13
It is lastly asserted (reply brief, page 4) that
[T]he "status register" of Brantley is identified
as part of the performance monitor chip (see page 195),
which is shown as a separate element from the processor
prototype and thus does not teach or suggest the use
of a machine state register . . .. So, again, even
the combination of Brantley with Wibecan does not
teach, show, or suggest Appellant's recited system
and utilization of a machine state register in
performance monitoring, including to identify a
selected event/specific address within a specific
process.
The examiner responds (answer, pages 4 and 5) that with
respect to allowing Wibecan's system to utilize a register to aid
in control functions, that allowing a register to store this bit
would not be detrimental to Wibecan's system because it is
suggested by Wibecan's disclosure that the Processor-Memory
Element (PME) is utilized to control the monitored process, and
that allowing this bit to be located in a register would have
been an obvious implementation of well known techniques already
practiced in the art, as shown by Brantley. With respect to
appellants' argument that Wibecan, Brantley and Gover do not show
the use of MMCRs or machine status registers to perform
performance monitoring based upon an effective address in a
specific process, the examiner takes the position (answer, page
6) that appellants' claims seem to lack this limitation as well.
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